Invention Grant
- Patent Title: Memory system
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Application No.: US18180944Application Date: 2023-03-09
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Publication No.: US11923029B2Publication Date: 2024-03-05
- Inventor: Marie Takada , Masanobu Shirakawa
- Applicant: Kioxia Corporation
- Applicant Address: JP Tokyo
- Assignee: Kioxia Corporation
- Current Assignee: Kioxia Corporation
- Current Assignee Address: JP Tokyo
- Agency: Oblon, McClelland, Maier & Neustadt, L.L.P.
- Priority: JP 21047628 2021.03.22
- The original application number of the division: US17471539 2021.09.10
- Main IPC: G11C29/42
- IPC: G11C29/42 ; G11C29/12 ; G11C29/18 ; G11C29/44 ; G11C29/50

Abstract:
According to one embodiment, a memory system includes: a controller configured to execute an error correction process on first data read from a first area at a first address of a memory device and determine a read level used for reading data at the first address according to a result of the correction process. The controller executes the correction process on first frame data of the first data. When the correction process on the first frame data has failed, the controller executes the correction process on second frame data of the first data. When the correction process on the second frame data has succeeded, the controller determines the read level based on a result of comparison between the second frame data and a result of the correction process on the second frame data.
Public/Granted literature
- US20230223097A1 MEMORY SYSTEM Public/Granted day:2023-07-13
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