- Patent Title: Signal generator for controlling timing of signal in memory device
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Application No.: US17857743Application Date: 2022-07-05
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Publication No.: US11923041B2Publication Date: 2024-03-05
- Inventor: Xiu-Li Yang , He-Zhou Wan , Mu-Yang Ye , Lu-Ping Kong , Ming-Hung Chang
- Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. , TSMC NANJING COMPANY LIMITED , TSMC CHINA COMPANY LIMITED
- Applicant Address: TW Hsinchu
- Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.,TSMC NANJING COMPANY LIMITED,TSMC CHINA COMPANY LIMITED
- Current Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.,TSMC NANJING COMPANY LIMITED,TSMC CHINA COMPANY LIMITED
- Current Assignee Address: TW Hsinchu; CN Nanjing; CN Shanghai
- Agency: Maschoff Brennan
- Priority: CN 2011311624.7 2020.11.20
- Main IPC: G11C7/00
- IPC: G11C7/00 ; G11C7/10 ; G11C7/12 ; G11C7/22

Abstract:
A device includes a memory array, bit line pairs, word lines, a modulation circuit and a control signal generator. The memory array has bit cells arranged in rows and columns. Each bit line pair is connected to a respective column of bit cells. Each word line is connected to a respective row of bit cells. The modulation circuit is coupled with at least one bit line pair. The control signal generator is coupled with the modulation circuit. The control signal generator includes a tracking wiring with a tracking length positively correlated with a depth distance of the word lines. The control signal generator is configured to produce a control signal, switching to a first voltage level for a first time duration in reference with the tracking length, for controlling the modulation circuit. A method of controlling aforesaid device is also disclosed.
Public/Granted literature
- US20220335992A1 SIGNAL GENERATOR FOR CONTROLLING TIMING OF SIGNAL IN MEMORY DEVICE Public/Granted day:2022-10-20
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