An arc flash mitigation system includes a main circuit protector such as a high amperage overcurrent protection fuse, and an arc flash mitigation network connected in parallel to the main circuit protector. The arc flash mitigation network includes at least one semiconductor switch operable to provide a shunt current path to a low amperage arc mitigation fuse for a faster response time to certain circuit conditions than the main circuit protector otherwise provides. The semiconductor switch may be a silicon controller rectifier operatively responsive to a voltage drop across the main circuit protector in use.