Invention Grant
- Patent Title: Semiconductor device
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Application No.: US17841203Application Date: 2022-06-15
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Publication No.: US11923296B2Publication Date: 2024-03-05
- Inventor: Naohito Suzumura , Kenichiro Sonoda , Hideaki Tsuchiya
- Applicant: RENESAS ELECTRONICS CORPORATION
- Applicant Address: JP Tokyo
- Assignee: RENESAS ELECTRONICS CORPORATION
- Current Assignee: RENESAS ELECTRONICS CORPORATION
- Current Assignee Address: JP Tokyo
- Agency: Rimon P.C.
- Priority: JP 21143196 2021.09.02
- Main IPC: H01L23/525
- IPC: H01L23/525
Abstract:
An interlayer dielectric layer covers an electric fuse element. A resistance layer made of silicon metal is arranged on the interlayer dielectric layer and directly above the electric fuse element.
Public/Granted literature
- US20230061976A1 SEMICONDUCTOR DEVICE Public/Granted day:2023-03-02
Information query
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