Invention Grant
- Patent Title: Die interconnect structures having bump field and ground plane
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Application No.: US17114954Application Date: 2020-12-08
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Publication No.: US11923308B2Publication Date: 2024-03-05
- Inventor: Zhiguo Qian , Kemal Aygun
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Akona IP PC
- Main IPC: H01L23/538
- IPC: H01L23/538 ; H01L23/00 ; H01L23/522 ; H01L23/528

Abstract:
Generally discussed herein are systems, devices, and methods to reduce crosstalk interference. An interconnect structure can include a first metal layer, a second metal layer, a third metal layer, the first metal layer closer to the first and second dies than the second and third metal layers, the first metal layer including a ground plane within a footprint of a bump field of the interconnect structure and signal traces outside the footprint of the bump field.
Public/Granted literature
- US20210167015A1 DIE INTERCONNECT STRUCTURES AND METHODS Public/Granted day:2021-06-03
Information query
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