Invention Grant
- Patent Title: Method of manufacturing semiconductor package
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Application No.: US17460284Application Date: 2021-08-29
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Publication No.: US11923318B2Publication Date: 2024-03-05
- Inventor: Tsung-Hsien Chiang , Hsien-Ming Tu , Hao-Yi Tsai , Tin-Hao Kuo
- Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicant Address: TW Hsinchu
- Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee Address: TW Hsinchu
- Agency: JCIPRNET
- The original application number of the division: US16285216 2019.02.26
- Main IPC: H01L23/544
- IPC: H01L23/544 ; B23K26/352 ; H01L21/48 ; H01L21/56 ; H01L23/00 ; H01L23/31 ; H01L23/538 ; B23K101/40

Abstract:
A method of manufacturing a semiconductor package includes the following steps. A backside redistribution structure is formed, wherein the backside redistribution structure comprises a first dielectric layer, and a redistribution metal layer over the first dielectric layer and comprising a dummy pattern. A semiconductor device is provided over the backside redistribution structure, wherein an active surface of the semiconductor device faces away from the backside redistribution structure, the semiconductor device is electrically insulated from the dummy pattern and overlapped with the dummy pattern from a top view of the semiconductor package. A front side redistribution structure is formed over the semiconductor device, wherein the front side redistribution structure is electrically connected to the semiconductor device. A patterning process is performed on the first dielectric layer to form a marking pattern opening exposing a part of the dummy pattern.
Public/Granted literature
- US20210391276A1 METHOD OF MANUFACTURING SEMICONDUCTOR PACKAGE Public/Granted day:2021-12-16
Information query
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