A clock data recovery circuit includes a phase detector, a first signal processing path, a second signal processing path, an oscillator circuit and a phase control circuit. The phase detector samples input data signal according to first clock signals to generate an up control signal and a down control signal. The first signal processing path includes at least one first signal processing device generating a phase control signal according to the up control signal and the down control signal. The second signal processing path includes at least one second signal processing device generating a frequency control signal according to the up control signal and the down control signal. The oscillator circuit generates second clock signals according to the frequency control signal. The phase control circuit controls phases of the second clock signals according to the phase control signal to generate the first clock signals.