Invention Grant
- Patent Title: Loop delay compensation in a delta-sigma modulator
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Application No.: US17380356Application Date: 2021-07-20
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Publication No.: US11929765B2Publication Date: 2024-03-12
- Inventor: Meghna Agrawal
- Applicant: TEXAS INSTRUMENTS INCORPORATED
- Applicant Address: US TX Dallas
- Assignee: Texas Instruments Incorporated
- Current Assignee: Texas Instruments Incorporated
- Current Assignee Address: US TX Dallas
- Agent Brian D. Graham; Frank D. Cimino
- Main IPC: H03M3/00
- IPC: H03M3/00 ; H03M1/12

Abstract:
A delta-sigma modulator includes a first integrator and a comparator. The comparator's positive input couples to the first integrator's positive output, and the comparator's negative input couples to the first integrator's negative output. A first current DAC comprises a current source device, and first and second transistors. The first transistor has a first transistor control input and first and second current terminals. The first current terminal couples to the current source device, and the second current terminal couples to the first integrator positive output. The second transistor has a second transistor control input and third and fourth current terminals. The third current terminal couples to the current source device, and the fourth current terminal couples to the first integrator negative output. A first capacitive device couples to the second transistor control input and to both the second current terminal and the first integrator positive output.
Public/Granted literature
- US20210351783A1 LOOP DELAY COMPENSATION IN A DELTA-SIGMA MODULATOR Public/Granted day:2021-11-11
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