A memory tester of the present embodiment includes a first memory, a second memory, an arithmetic circuit, and a determination circuit. The first memory is configured to store scan input data and expected value data, the scan input data including a don't care bit, the expected value data being obtained by converting the don't care bit into a first predetermined value. The second memory is configured to store scan output data and mask data obtained by converting a value of the scan input data other than the don't care bit into a second predetermined value. The arithmetic circuit is configured to perform an exclusive or operation between the expected value data and the scan output data. The determination circuit is configured to determine whether the don't care bit of an arithmetic result from the arithmetic circuit is passed or failed by using the mask data.