Invention Grant
- Patent Title: Lossless tiling in convolution networks-backward pass
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Application No.: US17384507Application Date: 2021-07-23
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Publication No.: US11934343B2Publication Date: 2024-03-19
- Inventor: Tejas Nagendra Babu Nama , Ruddhi Chaphekar , Ram Sivaramakrishnan , Raghu Prabhakar , Sumti Jairath , Junjue Wang , Kaizhao Liang , Adi Fuchs , Matheen Musaddiq , Arvind Krishna Sujeeth
- Applicant: SambaNova Systems, Inc.
- Applicant Address: US CA Palo Alto
- Assignee: SambaNova Systems, Inc.
- Current Assignee: SambaNova Systems, Inc.
- Current Assignee Address: US CA Palo Alto
- Agency: Flagship Patents
- Agent Bruce A. Young; Sikander M. Khan
- Main IPC: G06F15/78
- IPC: G06F15/78 ; G06F16/901 ; G06F17/16

Abstract:
Disclosed is a data processing system to receive a processing graph of an application. A compile time logic is configured to modify the processing graph and generate a modified processing graph. The modified processing graph is configured to apply a post-padding tiling after applying a cumulative input padding that confines padding to an input. The cumulative input padding pads the input into a padded input. The post-padding tiling tiles the padded input into a set of pre-padded input tiles with a same tile size, tiles intermediate representation of the input into a set of intermediate tiles with a same tile size, and tiles output representation of the input into a set of non-overlapping output tiles with a same tile size. Runtime logic is configured with the compile time logic to execute the modified processing graph to execute the application.
Public/Granted literature
- US20220309027A1 Lossless Tiling In Convolution Networks - Backward Pass Public/Granted day:2022-09-29
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