Invention Grant
- Patent Title: Smart relocation scan optimization
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Application No.: US17559802Application Date: 2021-12-22
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Publication No.: US11934706B2Publication Date: 2024-03-19
- Inventor: Raghavendra Gopalakrishnan , Kalpit Bordia
- Applicant: Western Digital Technologies, Inc.
- Applicant Address: US CA San Jose
- Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
- Current Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
- Current Assignee Address: US CA San Jose
- Agency: ArentFox Schiff LLP
- Main IPC: G06F3/06
- IPC: G06F3/06

Abstract:
Aspects of a storage device provide an optimized data relocation scanning process which significantly reduces a number of page reads performed during a block relocation scan by consolidating logical addresses for multiple FMUs in a single FMU. The storage device includes a memory comprising a block including pages and FMUs, and a controller that is configured to store, in one of the FMUs, logical addresses for multiple FMUs. The controller is further configured, in response to a data relocation command, to read the logical addresses from the FMU, to determine at least one of the read logical addresses is mapped to a current FMU in a L2P mapping table, and to relocate data stored at the valid logical addresses in response to the determination. As a result, latency and power consumption associated with data relocation may be significantly reduced and storage device performance may thus be improved.
Public/Granted literature
- US20230195389A1 SMART RELOCATION SCAN OPTIMIZATION Public/Granted day:2023-06-22
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