Invention Grant
- Patent Title: Compression of sparse tensors
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Application No.: US17643999Application Date: 2021-12-13
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Publication No.: US11941248B2Publication Date: 2024-03-26
- Inventor: Vamsi Krishna Nalluri , Sai Lalith Chaitanya Ambatipudi , Mrinal J. Sarmah , Rajeev Patwari , Shreyas Manjunath , Sandeep Jayant Sathe
- Applicant: Xilinx, Inc.
- Applicant Address: US CA San Jose
- Assignee: XILINX, INC.
- Current Assignee: XILINX, INC.
- Current Assignee Address: US CA San Jose
- Agency: Crawford Maunu PLLC
- Main IPC: G06F3/06
- IPC: G06F3/06

Abstract:
Approaches for data compression involve a compression circuit packing non-zero data elements of a succession of words of a plurality of blocks into packed words by packing non-zero data elements of one or more words of the succession in each packed word, and restricting each packed word to data elements of one uncompressed block. The compression circuit writes each packed word in a RAM and within a compressed address range associated with the uncompressed block when the packed word is full of non-zero data elements, or before the packed word is full if the next input word is of another uncompressed block.
Public/Granted literature
- US20230185451A1 COMPRESSION OF SPARSE TENSORS Public/Granted day:2023-06-15
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