- Patent Title: Combination scan management for block families of a memory device
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Application No.: US18118082Application Date: 2023-03-06
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Publication No.: US11941277B2Publication Date: 2024-03-26
- Inventor: Shane Nowell , Michael Sheperek , Larry J. Koudele , Vamsi Pavan Rayaprolu
- Applicant: MICRON TECHNOLOGY, INC.
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: Lowenstein Sandler LLP
- Main IPC: G06F12/00
- IPC: G06F12/00 ; G06F3/06

Abstract:
An example memory sub-system includes a memory device and a processing device, operatively coupled to the memory device. The processing device is configured to initiate a scan process on a plurality of block families of the memory device; responsive to determining, based on the scan process, that a first block family of the plurality of block families and a second block family of the plurality of block families meet a combining criterion, merge the first block family and the second block family; and responsive to determining that a terminating condition has been satisfied, terminate the scan process.
Public/Granted literature
- US20230205442A1 COMBINATION SCAN MANAGEMENT FOR BLOCK FAMILIES OF A MEMORY DEVICE Public/Granted day:2023-06-29
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