Invention Grant
- Patent Title: Semiconductor structure and testing method thereof
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Application No.: US17080625Application Date: 2020-10-26
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Publication No.: US11942380B2Publication Date: 2024-03-26
- Inventor: Ming-Shiang Lin , Chia-Cheng Ho , Chun-Chieh Lu , Cheng-Yi Peng , Chih-Sheng Chang
- Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
- Applicant Address: TW Hsinchu
- Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
- Current Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
- Current Assignee Address: TW Hsinchu
- Agency: Maschoff Brennan
- Main IPC: H01L29/417
- IPC: H01L29/417 ; G01R27/26 ; H01L21/283 ; H01L21/306 ; H01L21/324 ; H01L21/66 ; H01L29/66

Abstract:
A method includes forming a dummy pattern over test region of a substrate; forming an interlayer dielectric (ILD) layer laterally surrounding the dummy pattern; removing the dummy pattern to form an opening; forming a dielectric layer in the opening; performing a first testing process on the dielectric layer; performing an annealing process to the dielectric layer; and performing a second testing process on the annealed dielectric layer.
Public/Granted literature
- US20210057290A1 SEMICONDUCTOR STRUCTURE AND TESTING METHOD THEREOF Public/Granted day:2021-02-25
Information query
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