Invention Grant
- Patent Title: High density low power interconnect using 3D die stacking
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Application No.: US17582380Application Date: 2022-01-24
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Publication No.: US11942409B2Publication Date: 2024-03-26
- Inventor: Ferran Martorell , Prasad Subramaniam
- Applicant: MARVELL ASIA PTE, LTD.
- Applicant Address: SG Singapore
- Assignee: MARVELL ASIA PTE LTD
- Current Assignee: MARVELL ASIA PTE LTD
- Current Assignee Address: SG Singapore
- Main IPC: H01L23/48
- IPC: H01L23/48 ; H01L21/304 ; H01L21/66 ; H01L21/768 ; H01L23/498 ; H01L23/528 ; H01L25/065
Abstract:
An integrated circuit includes a first set of dies, each die comprising circuitry and a second set of interposer dies. At least two dies of the first set of dies are connected to each other via at least one of the interposer dies. The at least one of the interposer dies includes first connections connected to a first die of the first set of dies, second connections connected to a second die of the first set of dies, and buffers connected between the first connections and the second connections. The buffers are configured to condition signals between the first die and the second die.
Public/Granted literature
- US20220148957A1 HIGH DENSITY LOW POWER INTERCONNECT USING 3D DIE STACKING Public/Granted day:2022-05-12
Information query
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