Invention Grant
- Patent Title: Voltage level shifting with reduced timing degradation
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Application No.: US17521651Application Date: 2021-11-08
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Publication No.: US11942933B2Publication Date: 2024-03-26
- Inventor: Wilson Jianbo Chen , Aliasgar Presswala , Chiew-Guan (Kelvin) Tan
- Applicant: QUALCOMM Incorporated
- Applicant Address: US CA San Diego
- Assignee: QUALCOMM INCORPORATED
- Current Assignee: QUALCOMM INCORPORATED
- Current Assignee Address: US CA San Diego
- Agency: Loza & Loza, LLP
- Main IPC: H03K19/0185
- IPC: H03K19/0185 ; H03K3/037 ; H03K19/003

Abstract:
An aspect of the disclosure relates to an apparatus including a first field effect transistor (FET) including a first gate configured to receive a first input signal that varies in accordance with a first voltage domain; and a first inverter including a first input configured to receive a second input signal that varies in accordance with a second voltage domain, and a first output configured to generate a first output signal that varies in accordance with the second voltage domain, wherein the first output signal is based on the first and second input signals, and wherein the first FET and the first inverter are coupled in series between first and second voltage rails. Per another aspect, the apparatus includes additional circuitry to allow the apparatus to process signals in accordance with a third voltage domain.
Public/Granted literature
- US20230145180A1 VOLTAGE LEVEL SHIFTING WITH REDUCED TIMING DEGRADATION Public/Granted day:2023-05-11
Information query
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