Invention Grant
- Patent Title: Product-sum arithmetic device, product-sum arithmetic circuit, and product-sum arithmetic method
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Application No.: US17250299Application Date: 2019-07-04
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Publication No.: US11947929B2Publication Date: 2024-04-02
- Inventor: Hiroyuki Yamagishi
- Applicant: SONY CORPORATION
- Applicant Address: JP Tokyo
- Assignee: SONY CORPORATION
- Current Assignee: SONY CORPORATION
- Current Assignee Address: JP Tokyo
- Agency: CHIP LAW GROUP
- Priority: JP 18129329 2018.07.06
- International Application: PCT/JP2019/026716 2019.07.04
- International Announcement: WO2020/009201A 2020.01.09
- Date entered country: 2020-12-29
- Main IPC: G06F7/544
- IPC: G06F7/544 ; G06N3/04
Abstract:
An arithmetic device includes a comparison unit comparing voltage generated with charge stored in a storage unit with a threshold, and outputting an output signal at a timing when the voltage exceeds the threshold, and a timing extension unit extending an interval between timings at each of which the output signal is output.
Public/Granted literature
- US20210271452A1 PRODUCT-SUM ARITHMETIC DEVICE, PRODUCT-SUM ARITHMETIC CIRCUIT, AND PRODUCT-SUM ARITHMETIC METHOD Public/Granted day:2021-09-02
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