Sense amplifier layout designs and related apparatuses and methods. An apparatus includes a cross-coupled pair of pull-up transistors of a sense amplifier, a cross-coupled pair of pull-down transistors of the sense amplifier, and a pair of conductive lines electrically connecting the cross-coupled pair of pull-up transistors to the cross-coupled pair of pull-down transistors. The apparatus also includes a sense amplifier control transistors sharing a continuous active material with one of the cross-coupled pair of pull-up transistors or the cross-coupled pair of pull-down transistors. A method includes asserting a shared control gate terminal of sense amplifier control transistors sharing a continuous active material with the cross-coupled pair of pull-down transistors, applying a pre-charge voltage potential to the pair of conductive lines, electrically connecting memory cells to the pre-charged pair of bit lines, and amplifying electrical charges delivered to the pair of bit lines by the memory cells.