Invention Grant
- Patent Title: Wafer placement table
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Application No.: US17465943Application Date: 2021-09-03
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Publication No.: US11948825B2Publication Date: 2024-04-02
- Inventor: Kenichiro Aikawa , Hiroshi Takebayashi , Tatsuya Kuno
- Applicant: NGK INSULATORS, LTD.
- Applicant Address: JP Nagoya
- Assignee: NGK INSULATORS, LTD.
- Current Assignee: NGK INSULATORS, LTD.
- Current Assignee Address: JP Nagoya
- Agency: BURR PATENT LAW, PLLC
- Priority: JP 19121490 2019.06.28
- Main IPC: H01L21/683
- IPC: H01L21/683

Abstract:
A wafer placement table includes: an electrostatic chuck that is a ceramic sintered body in which an electrode for electrostatic adsorption is embedded; a cooling member which is bonded to a surface on an opposite side of a wafer placement surface of the electrostatic chuck, and cools the electrostatic chuck; a hole for power supply terminal, the hole penetrating the cooling member in a thickness direction; and a power supply terminal which is bonded to the electrode for electrostatic adsorption from the surface on the opposite side of the wafer placement surface of the electrostatic chuck, and is inserted in the hole for power supply terminal. The outer peripheral surface of a portion of the power supply terminal is covered with an insulating thin film that is formed by coating of an insulating material, the portion being inserted in the hole for power supply terminal.
Public/Granted literature
- US20210398840A1 WAFER PLACEMENT TABLE Public/Granted day:2021-12-23
Information query
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