Invention Grant
- Patent Title: Forming nitrogen-containing low-K gate spacer
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Application No.: US17660097Application Date: 2022-04-21
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Publication No.: US11948841B2Publication Date: 2024-04-02
- Inventor: Wan-Yi Kao , Chung-Chi Ko
- Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
- Applicant Address: TW Hsinchu
- Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee Address: TW Hsinchu
- Agency: Slater Matsil, LLP
- The original application number of the division: US16057308 2018.08.07
- Main IPC: H01L21/8234
- IPC: H01L21/8234 ; H01L21/02 ; H01L21/311 ; H01L21/3213 ; H01L27/088 ; H01L29/66

Abstract:
A method includes forming a dummy gate stack over a semiconductor region of a wafer, and depositing a gate spacer layer using Atomic Layer Deposition (ALD) on a sidewall of the dummy gate stack. The depositing the gate spacer layer includes performing an ALD cycle to form a dielectric atomic layer. The ALD cycle includes introducing silylated methyl to the wafer, purging the silylated methyl, introducing ammonia to the wafer, and purging the ammonia.
Public/Granted literature
- US20220246478A1 Forming Nitrogen-Containing Low-K Gate Spacer Public/Granted day:2022-08-04
Information query
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