Invention Grant
- Patent Title: Method for preparing semiconductor device structure with bottom capacitor electrode having crown-shaped structure and interconnect portion
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Application No.: US18108755Application Date: 2023-02-13
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Publication No.: US11948968B2Publication Date: 2024-04-02
- Inventor: Hung-Chi Tsai
- Applicant: NANYA TECHNOLOGY CORPORATION
- Applicant Address: TW New Taipei
- Assignee: NANYA TECHNOLOGY CORPORATION
- Current Assignee: NANYA TECHNOLOGY CORPORATION
- Current Assignee Address: TW New Taipei
- Agent Xuan Zhang
- The original application number of the division: US17137129 2020.12.29
- Main IPC: H01L21/02
- IPC: H01L21/02 ; H01L49/02

Abstract:
The present disclosure provides a method for preparing a semiconductor device structure. The method includes forming a capacitor contact over a semiconductor substrate, and forming a base layer over the capacitor contact. The method also includes forming a dielectric layer over the base layer, and performing a first doping process to form a first doped region in the dielectric layer. The method further includes etching the dielectric layer such that a sidewall of the dielectric layer is aligned with a sidewall of the first doped region, and removing the first doped region to form a first gap structure in the dielectric layer after the dielectric layer is etched. In addition, the method includes forming a surrounding portion along sidewalls of the dielectric layer and a first interconnect portion in the first gap structure by a deposition process.
Public/Granted literature
Information query
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