Invention Grant
- Patent Title: Load-aware ECMP with flow tables
-
Application No.: US18304068Application Date: 2023-04-20
-
Publication No.: US11949586B2Publication Date: 2024-04-02
- Inventor: Sachin Prabhakarrao Kadu
- Applicant: Avago Technologies International Sales Pte. Limited
- Applicant Address: SG Singapore
- Assignee: Avago Technologies International Sales Pte. Limited
- Current Assignee: Avago Technologies International Sales Pte. Limited
- Current Assignee Address: SG Singapore
- Agency: Foley & Lardner LLP
- Main IPC: H04L45/24
- IPC: H04L45/24 ; H04L45/00 ; H04L45/02 ; H04L45/42 ; H04L47/125

Abstract:
A semiconductor chip for implementing load-aware equal-cost multipath routing includes a number of ports and several pipes, each pipe being coupled to a portion of ports on the semiconductor chip, and a central unit consisting of a state machine and multiple databases. The databases contain information regarding a communication network including an overlay network and an underlay network, and the state machine is implemented in hardware and can determine at least one feature of the overlay network and a corresponding group of paths within the underlay network.
Public/Granted literature
- US20230269175A1 LOAD-AWARE ECMP WITH FLOW TABLES Public/Granted day:2023-08-24
Information query