Invention Grant
- Patent Title: Method and procedure for miniaturing a multi-layer PCB
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Application No.: US17946450Application Date: 2022-09-16
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Publication No.: US11950361B2Publication Date: 2024-04-02
- Inventor: Shaun Joseph Greaney , Robert Migliorino , Michael Liccone , Clint Smith
- Applicant: Veea Inc.
- Applicant Address: US NY New York
- Assignee: VEEA INC.
- Current Assignee: VEEA INC.
- Current Assignee Address: US NY New York
- Agency: THE MARBURY LAW GROUP, LLC
- The original application number of the division: US17313073 2021.05.06
- Main IPC: H05K1/02
- IPC: H05K1/02

Abstract:
A multiple layer printed circuit board (PCB) in which the cores (or core layers) are removed and replaced with prepreg layers, which provide structure integrity for the PCB. Such a multi-layer PCB may include signal layers, ground plane layers, inner signal layers, and a single core substrate layer. Each of the layers may be separated from the other layers by at least one prepreg substrate layer.
Public/Granted literature
- US20230017840A1 Method and Procedure for Miniaturing a Multi-layer PCB Public/Granted day:2023-01-19
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