Invention Grant
- Patent Title: Method and structure for forming stairs in three-dimensional memory devices
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Application No.: US17218117Application Date: 2021-03-30
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Publication No.: US11950418B2Publication Date: 2024-04-02
- Inventor: Xinxin Liu , Jingjing Geng , Zhu Yang , Chen Zuo , Xiangning Wang
- Applicant: YANGTZE MEMORY TECHNOLOGIES CO., LTD.
- Applicant Address: CN Wuhan
- Assignee: YANGTZE MEMORY TECHNOLOGIES CO., LTD.
- Current Assignee: YANGTZE MEMORY TECHNOLOGIES CO., LTD.
- Current Assignee Address: CN Wuhan
- Agency: BAYES PLLC
- The original application number of the division: US16727896 2019.12.26
- Main IPC: H10B43/30
- IPC: H10B43/30 ; H10B41/50 ; H10B43/27 ; H10B43/35 ; H10B43/50

Abstract:
Embodiments of a three-dimensional (3D) memory device and fabrication methods thereof are disclosed. In an example, a method for forming a 3D memory device includes the following operations. A dielectric stack is formed to have interleaved sacrificial layers and dielectric layers. A stair is formed in the dielectric stack. The stair includes one or more sacrificial layers of the sacrificial layers and one or more dielectric layers of the dielectric layers. The stair exposes one of the sacrificial layers on a top surface and the one or more sacrificial layers on a side surface. An insulating portion is formed to cover the side surface of the stair to cover the one or more sacrificial layers. A sacrificial portion is formed to cover the top surface of the stair. The sacrificial portion is in contact with the one of sacrificial layers. The one or more sacrificial layers and the sacrificial portion are replaced with one or more conductor layers.
Public/Granted literature
- US20210249438A1 METHOD AND STRUCTURE FOR FORMING STAIRS IN THREE-DIMENSIONAL MEMORY DEVICES Public/Granted day:2021-08-12
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