Provided is a method of making a circuit pattern. The method includes: Step (A): providing a master substrate comprising a first photosensitive layer containing photosensitive particles; Step (B): providing an energy beam to reduce metal ions in a predetermined area of the first photosensitive layer to form multiple first metal particles; Step (C): removing unreduced photosensitive particles by a fixer to obtain a master mask; wherein the first metal particles form a first predetermined pattern in the master mask; Step (D): providing a chip comprising a second photosensitive layer containing second photosensitive particles; Step (E): putting the master mask on the second photosensitive layer and providing an energy beam to reduce metal ions of an uncovered part of the second photosensitive layer to form multiple atomized second metal particles; Step (F): removing unreduced photosensitive particles by a fixer to obtain the circuit pattern having line spacing at picoscopic/nanoscopic scale.