Invention Grant
- Patent Title: Technology to provide accurate training and per-bit deskew capability for high bandwidth memory input/output links
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Application No.: US17009241Application Date: 2020-09-01
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Publication No.: US11954360B2Publication Date: 2024-04-09
- Inventor: Narasimha Lanka , Kuljit Bains , Lohit Yerva
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Jordan IP Law LLC
- Main IPC: G06F3/06
- IPC: G06F3/06 ; G06F11/10 ; G06F13/16 ; G06N20/00

Abstract:
Systems, apparatuses and methods may provide for technology that programs a plurality of seed values into a plurality of linear feedback shift registers (LFSRs), wherein the plurality of LFSRs correspond to a data word (DWORD) and at least two of the plurality of seed values differ from one another. The technology may also train a link coupled to the plurality of LFSRs, wherein the plurality of seed values cause a parity bit associated with the DWORD to toggle while the link is being trained. In one example, the technology also automatically selects the plurality of seed values based on one or more of an expected traffic pattern on the link (e.g., after training) or a deskew constraint associated with the link.
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