Invention Grant
- Patent Title: Encapsulation warpage reduction for semiconductor die assemblies and associated methods and systems
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Application No.: US17315588Application Date: 2021-05-10
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Publication No.: US11955345B2Publication Date: 2024-04-09
- Inventor: Brandon P. Wirz , Liang Chun Chen
- Applicant: Micron Technology, Inc.
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: Perkins Coie LLP
- Main IPC: H01L21/56
- IPC: H01L21/56 ; H01L21/48

Abstract:
Encapsulation warpage reduction for semiconductor die assemblies, and associated methods and systems are disclosed. In one embodiment, a semiconductor die assembly includes an interface die, a stack of semiconductor dies attached to a surface of the interface die, where the stack of semiconductor dies has a first height from the surface. The semiconductor die assembly also includes an encapsulant over the surface and surrounding the stack of semiconductor dies, where the encapsulant includes a sidewall with a first portion extending from the surface to a second height less than the first height and a second portion extending from the second height to the first height. Further, the first portion has a first texture and the second portion has a second texture different from the first texture.
Public/Granted literature
- US20220359230A1 ENCAPSULATION WARPAGE REDUCTION FOR SEMICONDUCTOR DIE ASSEMBLIES AND ASSOCIATED METHODS AND SYSTEMS Public/Granted day:2022-11-10
Information query
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