Invention Grant
- Patent Title: Semiconductor assemblies using edge stacking and methods of manufacturing the same
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Application No.: US17115710Application Date: 2020-12-08
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Publication No.: US11955457B2Publication Date: 2024-04-09
- Inventor: Thomas H. Kinsley
- Applicant: Micron Technology, Inc.
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: Perkins Coie LLP
- Main IPC: H01L25/065
- IPC: H01L25/065 ; H01L23/00 ; H01L23/053 ; H01L23/24 ; H01L23/31 ; H01L23/498 ; H01L23/522

Abstract:
Semiconductor assemblies and packages using edge stacking and associated systems and methods are disclosed herein. A semiconductor package may include (1) a base substrate having a base surface, (2) one or more dies attached over the base surface, and (3) a mold material encapsulating the base substrate and the one or more dies. The package may further include connectors on a side surface thereof, wherein the connectors are electrically coupled to the base substrate and/or the one or more dies. The connectors may be further configured to electrically couple the package to one or more neighboring semiconductor packages and/or electrical circuits.
Public/Granted literature
- US20210091039A1 SEMICONDUCTOR ASSEMBLIES USING EDGE STACKING AND METHODS OF MANUFACTURING THE SAME Public/Granted day:2021-03-25
Information query
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