Invention Grant
- Patent Title: Semiconductor assemblies with system and methods for aligning dies using registration marks
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Application No.: US17410327Application Date: 2021-08-24
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Publication No.: US11955461B2Publication Date: 2024-04-09
- Inventor: Shiro Uchiyama
- Applicant: Micron Technology, Inc.
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: Perkins Coie LLP
- Main IPC: H01L25/065
- IPC: H01L25/065 ; H01L21/50 ; H01L23/544 ; H01L25/00

Abstract:
Semiconductor device assemblies having features that are used to align semiconductor dies, and associated systems and methods, are disclose herein. In some embodiments, a semiconductor device assembly includes substrate that has a top surface and an alignment structure at the top surface. A first die is disposed over the top surface of the substrate, and the first die has a first channel that extends between a top side and a bottom side of the first die. The first channel is vertically aligned with and exposes the alignment structure at the top surface of the substrate.
Public/Granted literature
- US20230062701A1 SEMICONDUCTOR ASSEMBLIES WITH SYSTEM AND METHODS FOR ALIGNING DIES USING REGISTRATION MARKS Public/Granted day:2023-03-02
Information query
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