Invention Grant
- Patent Title: Depletion mode GaN transistor control circuit and corresponding method
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Application No.: US17893684Application Date: 2022-08-23
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Publication No.: US11955960B2Publication Date: 2024-04-09
- Inventor: Ke-Horng Chen , Tzu-Hsien Yang , Yong-Hwa Wen , Kuo-Lin Cheng
- Applicant: Chip-GaN Power Semiconductor Corporation
- Applicant Address: TW Hsinchu
- Assignee: CHIP-GAN POWER SEMICONDUCTOR CORPORATION
- Current Assignee: CHIP-GAN POWER SEMICONDUCTOR CORPORATION
- Current Assignee Address: TW Hsinchu
- Agency: WPAT, PC
- Main IPC: H03K19/003
- IPC: H03K19/003 ; H03K17/16

Abstract:
The invention uses the control circuit formed on the silicon wafer to detect the leakage current of transistor formed on the depletion mode GaN wafer and then adjust the gate voltage of the depletion mode GaN transistor according to the detected leakage current. Essentially, the gate voltage is reduced or viewed as made more negative when the detected leakage current is larger a specific value. Thus, the gate voltage can be gradually adjusted to approach a specific threshold voltage that right block the leakage current. In other words, by making the gate voltage more negative when non-zero leakage current is detected and even by making the gate voltage more positive when zero leakage current is detected, the depletion mode GaN transistor can be adjusted to have an acceptable or even zero leakage current, a high reaction rate and an optimized efficiency.
Public/Granted literature
- US20240072790A1 DEPLETION MODE GAN TRANSISTOR CONTROL CIRCUIT AND CORRESPONDING METHOD Public/Granted day:2024-02-29
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