Invention Grant
- Patent Title: 3D semiconductor devices and structures with transistors
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Application No.: US18234368Application Date: 2023-08-15
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Publication No.: US11956976B2Publication Date: 2024-04-09
- Inventor: Deepak C. Sekar , Zvi Or-Bach
- Applicant: Monolithic 3D Inc.
- Applicant Address: US OR Klamath Falls
- Assignee: Monolithic 3D Inc.
- Current Assignee: Monolithic 3D Inc.
- Current Assignee Address: US OR Klamath Falls
- Agency: Patent PC
- Agent Bao Tran
- Main IPC: H10B63/00
- IPC: H10B63/00 ; H01L21/268 ; H01L21/683 ; H01L21/762 ; H01L21/822 ; H01L21/84 ; H01L27/06 ; H01L27/12 ; H01L29/423 ; H01L29/78 ; H10B10/00 ; H10B12/00 ; H10B41/20 ; H10B41/41 ; H10B43/20 ; H10B61/00 ; H01L27/105 ; H10B41/40 ; H10B43/40 ; H10N70/00 ; H10N70/20

Abstract:
A semiconductor device including: a plurality of transistors, where at least one of the transistors includes a first single crystal source, channel, and drain, where at least one of the transistors includes a second single crystal source, channel, and drain, where the second single crystal source, channel, and drain is disposed above the first single crystal source, channel, and drain, where at least one of the transistors includes a third single crystal source, channel, and drain, where the third single crystal source, channel, and drain is disposed above the second single crystal source, channel, and drain, where at least one of the transistors includes a fourth single crystal source, channel, and drain, where the fourth single crystal source, channel, and drain is disposed above the third single crystal source, channel, and drain, and where the fourth drain is aligned to the first drain with less than 40 nm misalignment.
Public/Granted literature
- US20230397441A1 3D SEMICONDUCTOR DEVICES AND STRUCTURES WITH TRANSISTORS Public/Granted day:2023-12-07
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