Invention Grant
- Patent Title: Manufacturing method for integrating gate dielectric layers of different thicknesses
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Application No.: US17516589Application Date: 2021-11-01
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Publication No.: US11961740B2Publication Date: 2024-04-16
- Inventor: Lian Lu , Yizheng Zhu , Xiangguo Meng
- Applicant: SHANGHAI HUALI INTEGRATED CIRCUIT CORPORATION
- Applicant Address: CN Shanghai
- Assignee: SHANGHAI HUALI INTEGRATED CIRCUIT CORPORATION
- Current Assignee: SHANGHAI HUALI INTEGRATED CIRCUIT CORPORATION
- Current Assignee Address: CN Shanghai
- Agency: Alston & Bird LLP
- Priority: CN 2011201972.9 2020.11.02
- Main IPC: H01L21/28
- IPC: H01L21/28 ; H01L21/308 ; H01L21/67 ; H01L21/768

Abstract:
The present application discloses a method for manufacturing semiconductor devices having gate dielectric layers at different thickness. The gate dielectric layers having other than the minimum thickness are respectively formed by the following steps: step 1: forming a first mask layer; step 2: etching the first mask layer to form a first opening; step 3: etching a semiconductor substrate at the bottom of the first opening to form a second groove; step 4: filling the second groove and the first opening with the second material layer; step 5: etching back the second material layer to form the gate dielectric layer, such that the second material layer is flush with the top surface of the semiconductor substrate; and step 6: removing the first mask layer.
Public/Granted literature
- US20220139711A1 MANUFACTURING METHOD FOR INTEGRATING GATE DIELECTRIC LAYERS OF DIFFERENT THICKNESSES Public/Granted day:2022-05-05
Information query
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