Invention Grant
- Patent Title: Structure and process of integrated circuit having latch-up suppression
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Application No.: US17982163Application Date: 2022-11-07
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Publication No.: US11961769B2Publication Date: 2024-04-16
- Inventor: Kuo-Hsiu Hsu , Yu-Kuan Lin , Feng-Ming Chang , Hsin-Wen Su , Lien Jung Hung , Ping-Wei Wang
- Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
- Applicant Address: TW Hsin-Chu
- Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD
- Current Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD
- Current Assignee Address: TW Hsinchu
- Agency: HAYNES AND BOONE, LLP
- Main IPC: H01L21/8238
- IPC: H01L21/8238 ; G06F30/392 ; G11C11/412 ; H01L21/762 ; H01L27/092 ; H10B10/00

Abstract:
A method of forming an integrated circuit, including forming a n-type doped well (N-well) and a p-type doped well (P-well) disposed side by side on a semiconductor substrate, forming a first fin active region extruded from the N-well and a second fin active region extruded from the P-well, forming a first isolation feature inserted between and vertically extending through the N-well and the P-well, and forming a second isolation feature over the N-well and the P-well and laterally contacting the first and the second fin active regions.
Public/Granted literature
- US20230059973A1 Structure and Process of Integrated Circuit Having Latch-Up Suppression Public/Granted day:2023-02-23
Information query
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