Invention Grant
- Patent Title: Semiconductor structure having high breakdown voltage etch-stop layer
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Application No.: US17875464Application Date: 2022-07-28
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Publication No.: US11961803B2Publication Date: 2024-04-16
- Inventor: Joung-Wei Liou , Chin Kun Lan
- Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
- Applicant Address: TW Hsinchu
- Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee Address: TW Hsinchu
- Agency: Sterne, Kessler, Goldstein & Fox P.L.L.C.
- The original application number of the division: US16432569 2019.06.05
- Main IPC: H01L23/532
- IPC: H01L23/532 ; H01L21/02 ; H01L21/768

Abstract:
The present disclosure relates to a method of forming a semiconductor structure. The method includes depositing an etch-stop layer (ESL) over a first dielectric layer. The ESL layer deposition can include: flowing a first precursor over the first dielectric layer; purging at least a portion of the first precursor; flowing a second precursor over the first dielectric layer to form a sublayer of the ESL layer; and purging at least a portion of the second precursor. The method can further include depositing a second dielectric layer on the ESL layer and forming a via in the second dielectric layer and through the ESL layer.
Public/Granted literature
- US20230008675A1 HIGH BREAKDOWN VOLTAGE ETCH-STOP LAYER Public/Granted day:2023-01-12
Information query
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