Frequency-locked and phase-locked loop-based clock glitch detection for security
Abstract:
A glitch detection device includes an oscillator to generate multiple local clocks of multiple different phases and a sampling circuit to oversample, using the multiple local clocks, a system clock to generate multiple samples of the system clock. The device further includes digital logic that in turn includes a glitch detector to monitor a variation in pulse width of the system clock based on counting the multiple samples and to report a glitch in response to detecting a variation in the pulse width that exceeds a threshold value. The digital logic further includes a loop filter coupled between the glitch detector and the oscillator. The loop filter variably adjusts the oscillator based on a frequency of each of the multiple samples to control an output frequency of each of the multiple different phases of the oscillator.
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