Invention Grant
- Patent Title: Lithographic overlay correction and lithographic process
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Application No.: US17081800Application Date: 2020-10-27
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Publication No.: US11966170B2Publication Date: 2024-04-23
- Inventor: Ai-Jen Hung , Yung-Yao Lee , Heng-Hsin Liu , Chin-Chen Wang , Ying Ying Wang
- Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
- Applicant Address: TW Hsinchu
- Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
- Current Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
- Current Assignee Address: TW Hsinchu
- Agency: WPAT LAW
- Agent Anthony King
- The original application number of the division: US15992000 2018.05.29
- Main IPC: G03F7/20
- IPC: G03F7/20 ; G03F7/00 ; G03F9/00 ; H01L21/68

Abstract:
A method includes receiving a wafer, measuring a surface topography of the wafer; calculating a topographical variation based on the surface topography measurement performing a single-zone alignment compensation when the topographical variation is less than a predetermined value or performing a multi-zone alignment compensation when the topographical variation is greater than the predetermined value; and performing a wafer alignment according to the single-zone alignment compensation or the multi-zone alignment compensation.
Public/Granted literature
- US20210041792A1 LITHOGRAPHIC OVERLAY CORRECTION AND LITHOGRAPHIC PROCESS Public/Granted day:2021-02-11
Information query
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