Invention Grant
- Patent Title: Wafer stacking structure and manufacturing method thereof
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Application No.: US17396776Application Date: 2021-08-09
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Publication No.: US11967558B2Publication Date: 2024-04-23
- Inventor: Shou-Zen Chang , Chun-Lin Lu , Jium-Ming Lin
- Applicant: Powerchip Semiconductor Manufacturing Corporation , Jium-Ming Lin
- Applicant Address: TW Hsinchu
- Assignee: Powerchip Semiconductor Manufacturing Corporation,Jium-Ming Lin
- Current Assignee: Powerchip Semiconductor Manufacturing Corporation,Jium-Ming Lin
- Current Assignee Address: TW Hsinchu; TW Hsinchu
- Agency: JCIPRNET
- Priority: TW 0122035 2021.06.17
- Main IPC: H01L23/538
- IPC: H01L23/538 ; H01L21/48 ; H01L23/00 ; H01L23/552 ; H01L25/00 ; H01L25/10 ; H01Q1/22

Abstract:
A wafer stack structure includes an interlayer, a first wafer, and a second wafer. The interlayer has a first surface and a second surface opposite to the first surface. The intermediate layer includes a dielectric material layer and a redistribution layer embedded in the dielectric material layer. The first wafer is disposed on the first surface of the interlayer. The second wafer is disposed on the second surface of the interlayer. The second wafer is electrically connected to the first wafer through the redistribution layer of the interlayer.
Public/Granted literature
- US20220406722A1 WAFER STACKING STRUCTURE AND MANUFACTURING METHOD THEREOF Public/Granted day:2022-12-22
Information query
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