Invention Grant
- Patent Title: Method for manufacturing semiconductor device
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Application No.: US16967246Application Date: 2018-02-06
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Publication No.: US11977099B2Publication Date: 2024-05-07
- Inventor: Tomohisa Ohtaki , Takayuki Mizuno , Ryo Hirano , Toru Fujimura , Shigehiko Kato , Yasuhiko Nara , Katsuo Ohki , Akira Kageyama , Masaaki Komori
- Applicant: Hitachi High-Tech Corporation
- Applicant Address: JP Tokyo
- Assignee: Hitachi High-Tech Corporation
- Current Assignee: Hitachi High-Tech Corporation
- Current Assignee Address: JP Tokyo
- Agency: Crowell & Moring LLP
- International Application: PCT/JP2018/003987 2018.02.06
- International Announcement: WO2019/155519A 2019.08.15
- Date entered country: 2020-08-04
- Main IPC: G01R1/04
- IPC: G01R1/04 ; G01R31/28 ; H01L21/66

Abstract:
A method for manufacturing a semiconductor device in which probes and the layout of the electrode pads of a test element group (TEG) are associated is provided. As a semiconductor device is miniaturized, a scribe area on a wafer also tends to decrease. Accordingly, it is necessary to reduce the size of a TEG arranged in the scribe area, and efficiently arrange an electrode pad for probe contact. Thus, it is necessary to associate the probes and the layout of the electrode pad. According to the method, a layout of a TEG electrode pad corresponding to a plurality of probes arranged in a fan shape or probes manufactured by Micro Electro Mechanical Systems (MEMS) technology is provided.
Public/Granted literature
- US20210048450A1 Method for Manufacturing Semiconductor Device Public/Granted day:2021-02-18
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