Invention Grant
- Patent Title: Multi-segment FET gate enhancement detection
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Application No.: US18090861Application Date: 2022-12-29
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Publication No.: US11977403B2Publication Date: 2024-05-07
- Inventor: Vinayak Hegde , Rolly Baradiya , Ankur Chauhan
- Applicant: TEXAS INSTRUMENTS INCORPORATED
- Applicant Address: US TX Dallas
- Assignee: TEXAS INSTRUMENTS INCORPORATED
- Current Assignee: TEXAS INSTRUMENTS INCORPORATED
- Current Assignee Address: US TX Dallas
- Agent Charles F. Koch; Frank D. Cimino
- Priority: IN 2241001907 2022.01.13
- Main IPC: G05F1/26
- IPC: G05F1/26 ; G05F1/46 ; G05F1/56 ; G05F3/26
Abstract:
In examples, an apparatus includes a FET, first and second voltage-to-current circuits, a current selection circuit, and a comparator. The FET has first and second segments. The first segment has a first gate coupled to the first voltage-to-current circuit, a first source, and a first drain. The second segment has a second gate coupled to the second voltage-to-current circuit, a second source coupled to the first source, and a second drain coupled to the first drain. The current selection circuit has a current selection circuit output and first and second current selection inputs. The first current selection circuit input is coupled to the first voltage-to-current circuit. The second current selection circuit input is coupled to the second voltage-to-current circuit. The comparator has a comparator output and first and second comparator inputs, the first comparator input is coupled to the current selection circuit output.
Public/Granted literature
- US20230221742A1 MULTI-SEGMENT FET GATE ENHANCEMENT DETECTION Public/Granted day:2023-07-13
Information query
IPC分类:
