Invention Grant
- Patent Title: On-die termination configuration for a memory device
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Application No.: US17494701Application Date: 2021-10-05
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Publication No.: US11977751B2Publication Date: 2024-05-07
- Inventor: Eric J. Stave
- Applicant: Micron Technology, Inc.
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: Holland & Hart LLP
- Main IPC: G06F3/00
- IPC: G06F3/00 ; G06F3/06

Abstract:
Methods, systems, and devices for on-die termination configuration for a memory device are described. In some examples, a memory device may determine a connection option from a set of connections options for which an ODT pin of the memory device is configured. Each connection option may correspond to a termination configuration for a different pin, such as a command and address (CA) pin, a clock (CK) pin, or a chip select (CS). Based on the determined connection option, the memory device may identify a respective termination option for each of the different pins, such as a first termination option for the CA pin, a second termination option for the CK pin, and a third termination option for the CS pin, and configure each of the different pins according to the respective termination option for that pin.
Public/Granted literature
- US20230117882A1 ON-DIE TERMINATION CONFIGURATION FOR A MEMORY DEVICE Public/Granted day:2023-04-20
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