Invention Grant
- Patent Title: Utilizing structured sparsity in systolic arrays
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Application No.: US17107823Application Date: 2020-11-30
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Publication No.: US11977885B2Publication Date: 2024-05-07
- Inventor: Subramaniam Maiyuran , Jorge Parra , Ashutosh Garg , Chandra Gurram , Chunhui Mei , Durgesh Borkar , Shubra Marwaha , Supratim Pal , Varghese George , Wei Xiong , Yan Li , Yongsheng Liu , Dipankar Das , Sasikanth Avancha , Dharma Teja Vooturi , Naveen K. Mellempudi
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: INTEL CORPORATION
- Current Assignee: INTEL CORPORATION
- Current Assignee Address: US CA Santa Clara
- Agency: JAFFERY WATSON MENDONSA & HAMILTON LLP
- Main IPC: G06F9/30
- IPC: G06F9/30 ; G06F9/38 ; G06F15/80

Abstract:
An apparatus to facilitate utilizing structured sparsity in systolic arrays is disclosed. The apparatus includes a processor comprising a systolic array to receive data from a plurality of source registers, the data comprising unpacked source data, structured source data that is packed based on sparsity, and metadata corresponding to the structured source data; identify portions of the unpacked source data to multiply with the structured source data, the portions of the unpacked source data identified based on the metadata; and output, to a destination register, a result of multiplication of the portions of the unpacked source data and the structured source data.
Public/Granted literature
- US20210081201A1 UTILIZING STRUCTURED SPARSITY IN SYSTOLIC ARRAYS Public/Granted day:2021-03-18
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