Invention Grant
- Patent Title: Method to produce a multi-level semiconductor memory device and structure
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Application No.: US16797231Application Date: 2020-02-21
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Publication No.: US11978731B2Publication Date: 2024-05-07
- Inventor: Zvi Or-Bach , Jin-Woo Han
- Applicant: Monolithic 3D Inc.
- Applicant Address: US CA San Jose
- Assignee: Monolithic 3D Inc.
- Current Assignee: Monolithic 3D Inc.
- Current Assignee Address: US OR Klamath Falls
- Agency: Patent PC, PowerPatent
- Agent Bao Tran
- Priority: WO TUS2016052726 2016.09.21
- Main IPC: H01L25/00
- IPC: H01L25/00 ; H01L25/065 ; H10B20/00 ; H10B20/20 ; H10B41/10 ; H10B41/27 ; H10B41/35 ; H10B41/41 ; H10B43/10 ; H10B43/27 ; H10B43/35 ; H10B43/40 ; H10B63/00 ; H10N70/00

Abstract:
A method to process a 3D device, the method including: providing a first substrate including a first level including a first single crystal silicon layer and a plurality of first transistors; providing a second substrate including a second level including a second single crystal silicon layer; performing an epitaxial growth of a SiGe layer on top of the second single crystal silicon layer; performing an epitaxial growth of a third single crystal silicon layer on top of the SiGe layer; forming a plurality of third transistors including the third single crystal silicon layer; forming a plurality of metal layers interconnecting the plurality of third transistors; and then performing a hybrid bonding of the second level onto the first level.
Information query
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