Invention Grant
- Patent Title: Three-dimensional capacitive structures and their manufacturing methods
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Application No.: US17496185Application Date: 2021-10-07
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Publication No.: US11978766B2Publication Date: 2024-05-07
- Inventor: Frédéric Voiron , Julien El Sabahy , Hiroshi Nakagawa , Naoki Iwaji , Guy Parat
- Applicant: Murata Manufacturing Co., Ltd. , COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
- Applicant Address: JP Nagaokakyo
- Assignee: MURATA MANUFACTURING CO., LTD.,COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
- Current Assignee: MURATA MANUFACTURING CO., LTD.,COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
- Current Assignee Address: JP Nagaokakyo; FR Paris
- Agency: Arentfox Shiff LLP
- Priority: EP 305457 2019.04.08
- Main IPC: H01G4/12
- IPC: H01G4/12 ; H01G4/012 ; H01G4/30 ; H01G4/33 ; H01L23/00 ; H01L29/00 ; H01L49/02

Abstract:
Three-dimensional capacitive structures may be produced by forming a capacitive stack conformally over pores in a region of porous anodic oxide. The porous anodic oxide region is provided on a stack of electrically-conductive layers including an anodization-resistant layer and an interconnection layer. In the pores there is a position having restricted diameter quite close to the pore bottom. In a first percentage of the pores in the region of anodic oxide, a functional portion of the capacitive stack is formed so as to extend into the pores no further than the restricted-diameter position. Cracks that may be present in the anodization-resistant layer have reduced effect on the properties of the capacitive structure. Increased thickness of the anodization-resistant layer can be tolerated, enabling equivalent series resistance of the overall capacitive structure to be reduced.
Public/Granted literature
- US20220093726A1 THREE-DIMENSIONAL CAPACITIVE STRUCTURES AND THEIR MANUFACTURING METHODS Public/Granted day:2022-03-24
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