Invention Grant
- Patent Title: Oversampled phase lock loop in a read channel
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Application No.: US17958877Application Date: 2022-10-03
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Publication No.: US11979163B2Publication Date: 2024-05-07
- Inventor: Iouri Oboukhov , Derrick E. Burton , Richard Galbraith
- Applicant: Western Digital Technologies, Inc.
- Applicant Address: US CA San Jose
- Assignee: Western Digital Technologies, Inc.
- Current Assignee: Western Digital Technologies, Inc.
- Current Assignee Address: US CA San Jose
- Agency: Patent Law Works LLP
- Main IPC: H03L7/08
- IPC: H03L7/08 ; H03L7/091 ; H03L7/099

Abstract:
Example systems, read channels, and methods provide an oversampled digital phase lock loop for use in a read channel. The phase lock loop receives a digital data signal comprised of oversampled digital signal values with a sample rate that is a multiple of the baud rate of the channel. A set of oversampled digital signal values is selected for each iteration of the phase lock loop to correct the phase of an analog-to-digital converter. The phase lock loop determines a phase gradient, based on an iterative detector, and feeds back a phase correction for the next iteration of the phase lock loop. A baud rate digital data signal is provided to the rest of the channel based on down sampling or interpolated based on the phase gradient.
Public/Granted literature
- US20240120925A1 Oversampled Phase Lock Loop in a Read Channel Public/Granted day:2024-04-11
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