Invention Grant
- Patent Title: Verification of Ethernet hardware based on checksum correction with cyclic redundancy check
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Application No.: US17943712Application Date: 2022-09-13
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Publication No.: US11979232B2Publication Date: 2024-05-07
- Inventor: Jishnu De , Jaspreet Singh Gambhir
- Applicant: Synopsys, Inc.
- Applicant Address: US CA Mountain View
- Assignee: Synopsys, Inc.
- Current Assignee: Synopsys, Inc.
- Current Assignee Address: US CA Mountain View
- Agency: Fenwick & West LLP
- Main IPC: H04L1/00
- IPC: H04L1/00 ; H04L1/24 ; H04L43/106

Abstract:
A system performs verification of Ethernet hardware. A data frame including a first portion for storing a checksum value and a second portion for storing a timestamp value is received. The second portion of data frame is set to zero. A timestamp value for including in second portion of the data frame is received. A modified checksum value is determined based on the checksum value included in the first portion of the data frame and the timestamp value. A cyclic redundancy check (CRC) value is determined for the data frame by nullifying the checksum value in the data frame and considering the timestamp value. A final CRC value is determined by combining the CRC value for the data frame and a CRC correction value based on the checksum. The modified data frame is sent for processing using an emulator.
Public/Granted literature
- US20230086197A1 VERIFICATION OF ETHERNET HARDWARE BASED ON CHECKSUM CORRECTION WITH CYCLIC REDUNDANCY CHECK Public/Granted day:2023-03-23
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