A wire-line transceiver is configured to perform a serial loop back test. The wire-line transceiver includes an on-chip transmitter, an on-chip receiver and a fractional feed forward equalizer circuit (fractional FFE circuit) in a serial loop back line path between the on-chip transmitter and the on-chip receiver. The fractional FFE circuit is configured to induce a delay one of less than one symbol time of data, for enhancing an eye opening from the serial loop back line during the serial loop back test, compared to a situation where the fractional FFE circuit is not present or is not used.