Invention Grant
- Patent Title: CMOS over array of 3-D DRAM device
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Application No.: US17829939Application Date: 2022-06-01
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Publication No.: US11980021B2Publication Date: 2024-05-07
- Inventor: Sony Varghese , Fred Fishburn
- Applicant: Applied Materials, Inc.
- Applicant Address: US CA Santa Clara
- Assignee: Applied Materials, Inc.
- Current Assignee: Applied Materials, Inc.
- Current Assignee Address: US CA Santa Clara
- Agency: KDW Firm PLLC
- Main IPC: H10B12/00
- IPC: H10B12/00

Abstract:
Disclosed are 3-D DRAM devices and methods of forming 3-D DRAM devices. One method may include forming a stack of DRAM device layers, forming a MOS substrate directly atop the stack of alternating DRAM device layers, and forming a trench through the MOS substrate and the stack of DRAM device layers. The method may further include depositing a protection layer over the MOS substrate, wherein the protection layer is deposited at a non-zero angle of inclination relative to a vertical extending from a top surface of the MOS substrate.
Public/Granted literature
- US20220336470A1 CMOS OVER ARRAY OF 3-D DRAM DEVICE Public/Granted day:2022-10-20
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