Invention Grant
- Patent Title: Systems and methods for evaluating integrity of adjacent sub blocks of data storage apparatuses
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Application No.: US16457166Application Date: 2019-06-28
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Publication No.: US11984181B2Publication Date: 2024-05-14
- Inventor: Srinivasan Seetharaman , Sourabh Sankule , Piyush Girish Sagdeo
- Applicant: Western Digital Technologies, Inc.
- Applicant Address: US CA San Jose
- Assignee: Western Digital Technologies, Inc.
- Current Assignee: Western Digital Technologies, Inc.
- Current Assignee Address: US CA San Jose
- Agency: LOZA & LOZA, LLP
- Agent Gabriel Fitch
- Main IPC: G11C29/44
- IPC: G11C29/44 ; G06F11/20 ; G11C29/38 ; G11C29/04

Abstract:
The disclosure relates in some aspects to a design for a data storage apparatus with a non-volatile memory that includes a block of memory comprising N wordlines partitioned into a first sub-block comprising a first subset of the N wordlines and a second sub-block comprising a second subset of the N wordlines different than the first subset. In some aspects, the disclosure relates to detecting a failure in a first sub-block. The second sub-block is then marked, in response to a failure detection in the first sub-block, with an initial designation as an unusable sub-block, and a test of the second sub-block is performed to determine a usability of the second sub-block. Based on the test, the second sub-block is then marked with a second designation that is one of a tested usable sub-block or a tested unusable sub-block.
Information query