Invention Grant
- Patent Title: Semiconductor testing structure and method for forming same
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Application No.: US17453852Application Date: 2021-11-07
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Publication No.: US11984370B2Publication Date: 2024-05-14
- Inventor: Xiangyu Wang , Haibo Chen
- Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.
- Applicant Address: CN Hefei
- Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
- Current Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
- Current Assignee Address: CN Hefei
- Agency: Syncoda LLC
- Agent Feng Ma
- Priority: CN 2110777975.5 2021.07.09
- Main IPC: H01L21/66
- IPC: H01L21/66

Abstract:
A semiconductor testing structure forming method includes: a semiconductor substrate is provided, and the semiconductor substrate includes a plurality of active areas arranged separately; a first conductive wire is formed at a preset distance from the plurality of active areas in the semiconductor substrate, and the first conductive wire is connected with a substrate of a respective active device formed in each of the plurality of active areas; a plurality of first contact holes is formed on the first conductive wire; and a first metal layer is formed on top of each of the plurality of first contact holes to obtain the semiconductor testing structure, where the first metal layer is electrically connected with a first common pad and the first common pad is configured to perform an electric performance test on the semiconductor testing structure.
Public/Granted literature
- US20230008265A1 SEMICONDUCTOR TESTING STRUCTURE AND METHOD FOR FORMING SAME Public/Granted day:2023-01-12
Information query
IPC分类: