Invention Grant
- Patent Title: Stacked FET integration with BSPDN
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Application No.: US17304460Application Date: 2021-06-22
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Publication No.: US11984401B2Publication Date: 2024-05-14
- Inventor: Ruilong Xie , Junli Wang , Mukta Ghate Farooq , Dechao Guo
- Applicant: International Business Machines Corporation
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Agent Stephen R. Yoder
- Main IPC: H01L23/00
- IPC: H01L23/00 ; H01L21/02 ; H01L21/8238 ; H01L23/528 ; H01L27/092 ; H01L29/06 ; H01L29/417 ; H01L29/423 ; H01L29/66 ; H01L29/786

Abstract:
A semiconductor device including a hybrid contact scheme for stacked FET is disclosed with integration of a BSPDN. A double-sided (both frontside and backside of the wafer) contact scheme with buried power rail (BPR) and backside power distribution network (BSPDN) provides optimum contact and interconnect. The stacked FET could include, for example, FINFET over FINFET, FINFET over nanosheet, or nanosheet over nanosheet.
Public/Granted literature
- US20220406715A1 STACKED FET INTEGRATION WITH BSPDN Public/Granted day:2022-12-22
Information query
IPC分类: